1. Field of the Invention
The present invention relates to an information processing apparatus, and can be preferably applied to an interface unit with an in-circuit emulator (hereinafter referred to as an ICE) in a built-in type micro-controller.
2. Description of the Related Art
When an operation of the CPU is traced, it is necessary to externally output the trace data indicating the actual execution history.
On the other hand, for example, a RISC microcontroller provides an instruction bus and a data bus separately, and a bus width is designed for a larger number of bits so that the operations of the CPU can be performed at a higher speed.
It is hard to actually extend the width of a bus to output trace data based on the above described technology because of an increasing number of pins per package.
Therefore, when the bit width of an address and data used in a micro-controller is 8 or 16 bits for a low speed operation, all trace data can be easily output externally. However, when the bit width of an address and data used in a micro-controller is 32 or 64 bits for a high speed operation at 100 MHZ or more, it is hard to output all trace data externally.
To solve the above described problem, the following technology is applied to the conventional tracing device.
FIG. 1 is a block diagram of the configuration of the conventional tracing device.
In FIG. 1, 201 is a micro-controller, 202 is a CPU, 203 is a bus controller, 204 is a tracing module functioning as an interface circuit with an ICE 205, 205 is an ICE for receiving trace data which is an execution history of the micro-controller 201, and 206 indicates trace memory storing trace data.
211 is an instruction address bus used by the CPU 202 in fetching an instruction. 212 is a data address bus used by the CPU 202 in accessing data. 213 is a data bus used by the CPU 202 in accessing data. 214 is an external bus of the micro-controller 201. 215 is a trace bus for outputting an instruction execution status of the CPU 202 to the ICE 205. 216 is a status output bus for outputting a signal indicating the status of the data output from the trace bus 215. 217 is a signal line for outputting a wait signal for stopping the CPU 202 when the output of the trace data from the trace bus 215 is delayed.
Assuming that the bit width of the instruction address bus 211, the instruction address bus 212, the data bus 213, and the trace bus 215 is 32 bits, the tracing module 204 outputs only the instruction address output from the instruction address bus 211 to the ICE 205 through the trace bus 215, and the trace data of only the instruction address is output for each clock. In this case, data access information output from the data address bus 212 and the data bus 213 is not output to the ICE 205.
On the other hand, when there is a request to simultaneously trace data access information and an instruction address, the tracing module 204 outputs data access information and an instruction address to the trace bus 215. When instruction access and data access simultaneously arise, the tracing module 204 sets on the CPU 202 a wait for the end of the output of the trace data to prevent the trace data from being lost because the trace bus 215 does not have a sufficient bus width for both access.
FIG. 2 is a block diagram of another configuration of the conventional tracing device.
In FIG. 2, 221 is a micro-controller, 222 is a CPU, 223 is a bus controller, 224 is a debug support unit (hereinafter referred to as a DSU) functioning as an interface circuit with an ICE 225, 225 is an ICE, and 226 is trace memory storing trace data. 231 is an instruction address bus for use by the CPU 222 fetching an instruction, 232 is a data address bus for use by the CPU 222 accessing data, 233 is a data bus for use by the CPU 222 accessing data, 234 is an external bus of the micro-controller 221, 235 is a trace bus for outputting an instruction execution status of the CPU 222 to the ICE 225, 236 is a status output bus for outputting a signal indicating the status of the data output from the trace bus 235, and the internal status of the micro-controller 221, 237 is a signal line notifying the DSU 224 that the CPU 222 has executed the instruction and executed a branch instruction.
FIG. 3 is a block diagram of the configuration of the DSU 224 shown in FIG. 2.
In FIG. 3, 241 is a buffer for holding an instruction address output from the instruction address bus 231, 242 is a buffer for holding a data address output from the data address bus 232, 243 is a buffer holding the data output from the data bus 233, 244 is a switch for selecting the data output from among the buffers 241 through 243 to the trace bus 235, 245 is a buffer for holding the data selected by the switch 244, 246 is a parallel-serial converter for serially outputting the data held by the buffer 245 to the trace bus 235, 247 is a control circuit for controlling the switch 244 after determining the data output depending on the statuses of the buffers 241 through 243 and the status of the parallel-serial converter 246, and 248 is an address decoder for detecting the data write to a specific address.
With the configuration, the number of clocks required to output data is fixed in the DSU 224 depending on the type of the data output from the trace bus 235, and the output of data is not aborted in the middle of the outputting process.
In addition, since the bus width of the trace bus 235 is not sufficient when data access is traced, only the information about the data write to an assignment address of the buffer 243 specified by the user program is selected by the address decoder 248, and output to the trace bus 235.
Furthermore, the DSU 224 receives information from the CPU 222 about the execution of an instruction and a branch instruction performed by the CPU 222. Then, the DSU 224 outputs a branched-to address from the trace bus 235, and constantly outputs from the status output bus 236 a status for counting the number of execution instructions by the ICE 225. Upon receipt of the branched-to address and the number of execution instructions from the DSU 224, the ICE 225 computes the branched-from instruction address and the branched-to instruction address when a branch occurs, and restores the execution history of the user program.
When only instruction execution is traced in the tracing device shown in FIG. 1, no wait is set on the CPU 202. However, when not only instruction execution but also data access is simultaneously traced, a wait can be set on the CPU 202. Therefore, the speed of operations of the CPU 202 depends on whether or not a tracing process is performed. For example, if a motor is controlled using the micro-controller 201 or serial communications are established, the CPU 202 can normally perform a process when no tracing operation is performed, but the process speed of the CPU 202 cannot be sufficiently high when a tracing operation is performed.
In addition, in the tracing device shown in FIG. 2, when the micro-controller 221 is operated in real time, information overflows the buffers 241 through 243 if branches occur at intervals of the number of clocks required for one branch information outputting operation, or if a user performs several data writing operations within a short time at an address specified by the address decoder 248 for debugging. Therefore, the information overflowing the buffers 241 through 243 cannot be output to the ICE 225 side, whereby incurring the problem that instruction execution cannot be traced.
Furthermore, since trace data is serially output from the trace bus 235, there arises the problem that the band width of the trace bus 235 is not sufficient for tracing data access, and only the information about the data write can be output to an address of the buffer 243 assigned by the user program.
Additionally, the status information output from the status output bus 236 is generated in synchronization with the information of the signal line 237 connected to the CPU 202. Accordingly, there has been the problem that the number of execution instructions output from the status output bus 236 is output in asynchronization with a branched-to address output from the trace bus 235, and that the process of computing the branched-from instruction address and the branched-to instruction address on the ICE 225 side according to the above described information is complicated.
In addition, the built-in type micro-controller 221 has to perform a debugging process in the final program format even when an applied product is being developed. Therefore, the DSU 224 shown.in FIG. 2 has the problem that an instruction code of data write for monitoring data is left in the final user program.
The present invention aims at providing an information processing apparatus capable of efficiently outputting trace data.
According to an aspect of the present invention, branch information is output after being inserted in an output sequence of data access information.
Thus, it is possible to commonly use an output bus for outputting data access information as an output bus for outputting branch information. Since it is not necessary to separately provide an output bus for outputting data access information and an output bus for outputting branch information, the size of the system can be reduced when a tracing operation is performed.
According to another aspect of the present invention, when a conflict between an output of branch information and an output of data access information is detected, the data access information is output after outputting the branch information.
Thus, even when branch information is inserted in an output sequence of data access information, it is possible to maintain the consistency in timing between branch information and data access information, thereby efficiently analyzing a tracing process.
According to a further aspect of the present invention, an instruction canceled by the generation of a branch is not output.
Thus, even when there arises a conflict between the output of branch information and the output of data access information, the information overflowing by the conflict can be received at the position where the instruction has been canceled, thereby reducing the load of the buffer for holding the overflowing information.
In addition, according to a further aspect of the present invention, the displacement of an address by the generation of a branch and the number of instruction executing operations from the generation of the branch to the generation of the next branch are computed, and only the number of significant digits of the address displacement and the number of instruction executing operations are output.
Thus, if the numbers of digits of the branched-from address and the branched-to address are large because the program is positioned around the end of the address space although the branched-from address and the branched-to address are not so separated, these pieces of information can be compressed, and the information can be output at a high speed.
According to a further aspect of the present invention, the number of significant digits can be contained in the branch information.
Thus, even if data in which the higher order bits of trace data are only 0 is not output, the branched-from address and the branched-to address can be restored. Therefore, the data in which the higher order bits of trace data are only 0 does not have to be output, thereby possibly compressing the trace data.
In addition, according to a further aspect of the present invention, a relative address and an absolute address are switched with each other and output based on the comparison between the number of significant digits of the relative address after a branch and the number of significant digits of the absolute address after a branch.
Thus, if the number of significant digits of a relative address becomes large because a branched-from address is separate from a branched-to address, then the relative address is not output as branch information, but the absolute address can be output as is as branch information, and the trace data can be efficiently analyzed in the ICE.
According to a further aspect of the present invention, only the numbers of significant digits of data address and access data can be output as data access information.
Thus, for example, when data is stored at an early stage in an address space, a redundant portion can be efficiently truncated and output, thereby outputting the information at a high speed.
According to a further aspect of the present invention, an absolute address is output at least once in a predetermined period.
Thus, a branch address chain can be traced from the point at which an absolute address is output in an instruction executing process. As a result, even when an address chain is broken during the process by losing data while a relative address is being output, the trace data can be analyzed from the point at which an absolute address is output, and the number of trace-back operations can be reduced when an absolute address is restored from a relative address, thereby easily generating a trace list.
According to a further aspect of the present invention, data read from an output timing adjusting buffer is output while being parallel-serial converted, and the decoding result of the data is simultaneously output as a status signal of a trace bus.
Thus, trace data and a signal indicating the status of the trace data can be synchronously output, thereby efficiently analyzing the trace data.
According to a further aspect of the present invention, in addition to a first output bus for use in parallel-serial converting and outputting trace data, a second output bus for use in outputting the trace data as parallel is provided. When the trace data is output through the second output bus, only an absolute address is output as branch information.
Thus, trace data can be output without being lost even when the trace data is not compressed.
According to a further aspect of the present invention, when branch information and data access information are output through the second output bus, system information other than the branch information and the data access information can be output through the first output bus.
Thus, trace data can be output without being lost, and the first output bus can be effectively used for use in outputting a status of a device, etc.
According to a further aspect of the present invention, when a buffer for adjusting an output timing becomes full, writing data to a buffer can be suspended after writing a data loss status to the buffer.
Thus, when data is lost, the data already written to a buffer before the data has been lost can be protected, and the position where the data has been lost can be confirmed, thereby efficiently tracing the data.
In addition, according to a further aspect of the present invention, writing data to a buffer after data has been lost is resumed at the occurrence of a branch, and an absolute address is written to a buffer as branch information.
Thus, a data chain can be traced from the starting point of resuming a data write, thereby preventing wasteful data from being written when the data write is resumed, thereby efficiently tracing data.
According to a further aspect of the present invention, a buffer is used as trace memory.
Thus, the amount of data equal to the capacity of a buffer can be prevented from being lost, thereby protecting the trace data and guaranteeing a debugging process on the trace data without a loss of data.